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Ultrasparc III Passes Physical Verification
By Ward Vercruysse and John Ferguson
Integrated System Design
February 1, 2002 (3:35 p.m. EST)
Since 1990, Sun Microsystems has tracked factors affecting design complexity and productivity with an extensive set of indicators. Based on this information, Sun constructed and adopted a methodology to avoid obstacles confronting IC design today. This methodology emerged as Sun grappled with the unique challenges of the Ultrasparc III processor. This processor employs a 600-MHz, 64-bit superscalar chip design for 1,000-way scalable systems, and presented formidable physical verification challenges.
This article discusses the decisions made by Sun to garner the needed physical verification solutions for today's state-of-the art IC designs.
In 1991, Sun's IC design team used a design flow with approximately 40 tools. Four years later, the number of tools topped 100, and by 1999 it had grown to a staggering 250 tools. Sun's figures for batch jobs per month ramped quickly from 10k in 1991 to over 1M in 1999. During the same time frame, the size of the design team grew by a factor of 10. The accompanying tables reveal the explosive growth in chip design and design tools and data.
Because of the design size and increased performance demands of the Ultrasparc III processor, Sun's physical verification flow needed a major upgrade. Sun employed an understanding of interdependent design complexities in its overall design methodology to develop a set of benchmarks for selecting a physical verification tool.
The main process design challenge is to make optimal use of the die area and power budget to achieve highest performance. For Sun's Ultrasparc III processor, that meant the highest frequency possible, the smallest transistors possible, low voltage, high currents and abundant dynamic logic.
In addition, design decisions that once were considered independently now were overlapped. The walls between logical, electrical and physical design collapsed. Previously, vertical design strategy assumed that a single hierarchy was suitable for all aspects of design. Today, parallel data hierarchies-behavioral, logical and physical-must be considered interdependently. Infrastructures, such as clock, power and repeaters, must be analyzed and designed in a way that handles complexities while reducing delays in instruction processing and eliminating interference in signal transmission. The Ultrasparc III project relied on more-accurate, multidimensional analysis of a wider variety of data.
It quickly became apparent that trade-offs, compromises and questions would occur throughout the design process. Typical issues and considerations faced by Sun's engineers included: Balancing the desire for smaller device size and high performance against rising costs.
Trading in the desire to use time-saving cell libraries for handcrafting necessary design elements;
or, trade-offs between using time-saving cell libraries or handcrafting necessary design elements.
Accommodating the need for a menu of library elements to meet varying requirements. For example, instead of employing a single "nand2" standard cell throughout, several cell versions with varying drive strengths are employed.
Weighing how much flop/latch placement should be constrained to minimize clock skew against minimizing signal delays.
Sun also faced the issue of modern design hierarchy. No longer top-down, bottom-up or meet-in-the-middle, IC design had become a convergence of iterations-nonlinear, abstractive, repetitive modeling and revision. With more components being placed on the die, more physical verification runs were required across all levels and abstractions. The physical verification tool had to be fast, provide efficient and dynamic recognition of repetitive components (cells, macros, etc.), and clearly identify errors.
Selection process
Sun adopted a design philosophy that maximized productivity in order to be first to market with a comprehensive set of features in its new processor design. Sun's method embraced high-performance tools that enhance productivity and are easily deployed throughout the central compute infrastructure. This gave it the ability to apply design and tool standards consistently across projects; automate where possible to accelerate design; handcraft unique components as needed; and correct by construct with continuous improvement through iterations, including full-chip integrations, flow work with dirty data and step-by-step verification and analysis.
Sun's designers expected the physical verification tool to work within an iterative, design-in-release context, adaptable to continuous refinement of release criteria. In Sun's design process, each segment has dedicated flows. Development stages are conducted in parallel flow rather than linear, avoiding the wait for completion of first-stage design blocks before later stages can be created. In this parallel process, the full chip design components are created with only estimations of what will be in the midsize and smallest building blocks. Sometimes "black boxes" represent this data, other times real blocks are used that have not yet passed verification.
Throughout the design process, interactions take place in convergent fashion through smart iterations, producing quick results based on estimations and "what if" scenarios. Physical blocks are released bottom-up, with each design step accompanied by a verification step. Many of the currently available physical verification tools run quickly on clean data, but when there are significant actual errors (as could easily be the case in an iterative, parallel design flow), these tools run significantly slower.
This environment drove Sun to a CAD strategy that made exceptions tractable and allowed flexibility without sacrificing efficiency.
A simple, nine-point strategy established reliable criteria for evaluating and incorporating EDA tools in the design process:
1. Standards. All tools must support open standards to allow efficient leveraging of vendor resources and easy integration within Sun's design flow.
2. Observable flexibility. Tools must demonstrate the ability to operate within all iterative, analytical and corrective parameters of the pipelined design environment.
3. Late binding. Tools must automatically adapt to changing hardware constructs, allow faster, simpler design verification by eliminating the need to modify rule files as designs evolve and enable efficiencies of leading-edge automation through compatibility with modern compute farms.
4. Stateless system for pipelined design. Designers need to access various versions of a design simultaneously without placing data on hold or having to maintain the data at each design step. A tool should not possess any hard-coded paths, links or central switches that could catch designers off-guard.
5. Resource sharing and optimization. Tools must allow maximum usage across computing resources and be compatible with other tools. This enables optimal run-time efficiency and flexibility, and avoids single points of failure.
6. Lightweight and batch-oriented operations. A tool cannot create a heavy footprint or place a burden on computing resources. The tool must also allow batches to be managed and processed at times optimal for network computational operations across a compute farm.
7. Data-centric environment. Tools must operate in a data-centric, vendor-independent environment, in which a single manufacturing database provides data to the various tools in the assembly and test process. This gives Sun the ability to change individual applications without adversely impacting the entire operation. Compute-intensive jobs run in a managed network resource (compute farm). Vendor formats are generally maintained; exceptions are translated into Sun's standards.
8. Build methodology into flows. Sun employs an incremental, hierarchical approach to design process and tool use, paralleling development stages. This helps avoid the slowdown that occurs in later stages of linear block creation.
9. Procure best-of-breed tools. Best-of-breed tools are imperative for successful achievement of design and market goals. Selecting a tool that is also easy to manage is critical. Sun's driving procurement philosophy is to "buy the right tools and to buy the tools right."
In benchmarking and qualifying a physical verification tool for the Ultrasparc III processor project, Sun considered three core criteria:
Functionality: ability to deal with dirty data, fit within Sun's hierarchical design methodology and avoid the limitations of incremental design rule check (DRC) runs characteristic of previous tools.
Performance: meet a 12-hour turnaround time.
Capacity: accommodate 29M transistors, 124 libraries and 170,000 cells.
Also chief among concerns was gaining the ability to run physical verification in 64-bit mode in the Sun Solaris operating environment.
Although Sun had been understandably cautious about replacing familiar tools that had been in place for many years, the physical verification tool that satisfied, and in many instances exceeded, benchmark requirements was Mentor Graphics' Calibre tool.
Sun decided to upgrade the physical verification tool and place Calibre into the design flow very quickly. With a company as large as Sun, the cost and effort of adopting a new tool is usually underestimated. But with Calibre, Sun overestimated-completing the process in just eight months.
This was possible for two reasons: Sun articulated straightforward evaluation criteria and prepared unambiguous test cases, conveying clear objectives and requirements; and Mentor Graphics provided dedicated training and expert Calibre application engineers throughout the process.
Calibre, with its advanced hierarchical processing engine, proved to be the only physical verification tool to automatically analyze design steps and optimize repetitive design hierarchy while boosting verification speed. For instance, once design libraries were done and verified using Calibre, they were transferred to a central area where Calibre reverified the library components. During the library development flow, cells and other circuit components were verified up to five times in an effort to reduce risk of failure and eliminate errors.
Calibre had to verify all components-individual cells, megacells, data paths, control blocks, SRAMS and clusters-as well as the full chip. It had to handle dirty data without a performance hit. Sun's design process required that the physical verification tool maintain low overhead on small jobs, yet be scalable so that larger jobs could be handled quickly.
Sun's application of Calibre anticipates the future. Calibre's 64-bit capability, utilization of Solaris 8 and ability to interface with Simplex tools for parasitic extraction with back annotation all help Sun meet rapidly evolving IC design challenges.
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Senior CAD architect Ward Vercruysse managed the Ultrasparc III design at Sun Microsystems (Mountain View, Calif.). John Ferguson, technical marketing manager at Mentor Graphics (Wilsonville, Ore.), holds a PhD in EE from Oregon Graduate Institute of Science and Technology.
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Copyright © 2002 CMP Media LLC
2/1/02, Issue # 14152, page 38.
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